1. Technical Field
The present invention generally relates to a method for fabricating a semiconductor device, and more particularly, to a transistor including a bulb-type recess channel and a method for fabricating the same.
2. Description of the Related Art
With the increase of integration of semiconductor devices, there is a requirement for a memory array transistor with sub-100 nm design rule. The sub-100 nm array transistor has very low threshold voltage due to the short channel effect, and thus a data retention time is gradually decreased.
A transistor having a recess channel has been developed to overcome the above limitation. The transistor having the recess channel has a long data retention time because a channel length is longer than that of a typical planar type transistor.
Recently, a method for extending the recess channel length has been proposed to obtain improved data retention time characteristics and improved current characteristics compared to a typical transistor having a recess channel. To this end, a bottom portion of a trench in the recess channel is additionally etched in the shape of a ball to thereby form a so-called bulb-type recess channel array transistor (BRCAT).
FIG. 1 illustrates a cross-sectional view of a typical method for forming a transistor including a bulb-type recess channel. A bulb-type recess pattern 12, configured with a trench pattern 12A and a ball pattern 12B, is formed in a substrate 11. A gate insulating layer 13 is formed over a surface of bulb-type recess pattern 12. A gate conductive layer 14 to be used as a gate electrode is formed over gate insulating layer 13 such that gate conductive layer 14 fills bulb-type recess pattern 12. Gate conductive layer 14 may include a polysilicon.
In the typical bulb-type recess channel, however, since the diameter of ball pattern 12B is greater than the width of trench pattern 12A in bulb-type recess pattern 12, gate conductive layer 14 does not completely fill ball pattern 12B when forming gate conductive layer 14. Therefore, a void V is often formed in the center of gate conductive layer 14 in ball pattern 12B.
In particular, void V may move toward gate insulating layer 13 while gate conductive layer 14 is being recrystallized by a subsequent high temperature thermal process. Consequently, a portion of gate insulating layer 13 may not be in contact with gate conductive layer 14 where void V exists.
FIG. 2 illustrates a cross-sectional view showing a state where void V moves toward gate insulating layer 13 of ball pattern 12B after a high temperature thermal process. The high temperature thermal process may be performed in a temperature range of approximately 650° C. to approximately 1,050° C. Gate conductive layer 14 may include a polysilicon.
Void V formed in the center of gate conductive layer 14 in ball pattern 12B moves toward gate insulating layer 13 to be in contact with gate insulating layer 13. The reason void V moves during the subsequent high temperature thermal process because a vacancy dissolved in gate conductive layer 14 at an equilibrium state causes void V in the center of gate conductive layer 14 in ball pattern 12B to grow and move during the high temperature thermal process. The vacancy refers to a type of lattice defect where atoms are dislodged from normal lattice positions in a crystal, which is also called an empty lattice point or a vacancy lattice point.
The reason for the vacancy movement is that the thickness of the polysilicon layer, i.e., gate conductive layer 14, in trench pattern 12A is greater than that in ball pattern 12B. That is, since the thickness of the polysilicon layer tends to become uniform while being recrystallized during the subsequent thermal process, the void in the polysilicon layer also moves correspondingly, resulting in changing the thickness of the polysilicon layer in ball pattern 12B.